1. Field of the Invention
This invention relates to a bias circuit having process variation compensation in a current source topology to produce a predetermined level of bias current.
2. Description of the Related Art
One of the more important requirements in many semiconductor circuits is the establishment of stable and predictable dc operating conditions. These conditions are provided and maintained by biasing circuits that control currents and/or voltages and thereby establish the operating points of the active transistors in the biased circuits.
The biasing circuits in turn can include various transistors whose characteristics must be predictable and subject to minimal variation with respect to external factors that can affect performance. These factors include process variations and power supply variations. With respect to process variations, the integrated-circuit manufacturing process can yield substantial differences in the parameters governing the current/voltage characteristics of a biasing transistor that directly controls the current or voltage output of the biasing circuit.
The threshold voltage (aka. pinchoff voltage), commonly abbreviated as Vth (Vpo), of a field-effect transistor (FET) is the minimum gate-to-source voltage differential (Vgs) that is needed to create a conducting channel between the source and drain terminals. A FET generally has three different regions/modes of operation, namely the linear region, knee region, and saturation region. For an n-channel device, the linear region begins when Vgs>Vth and is sometimes referred to as the ohmic mode, where it behaves like a voltage-controlled variable resistor. In the saturation region, Vgs>>Vth and the transistor functions more like a voltage-controlled (Vgs) current source where the channel current is mainly dependent on Vgs and not Vds. The knee region is a transition region between the linear and saturated regions.
Process variations can cause significant variation in Vth, either above or below a nominal value, which can affect either the current produced in saturation mode or the value of the resistance in the linear mode at a specific Vgs. Problems due to process variations are particularly acute when the channel current of the biasing transistor must be finely controlled. The magnitude of this current has a direct bearing on the operation of the circuit element that is biased by it. Therefore, it is important to establish a known bias level that can be maintained even with lot-to-lot variations in the manufacturing process.
A typical bias circuit includes a field-effect transistor (FET) operating in saturation mode as a current source to produce a predetermined level of bias current. The level is set by a predetermined gate-source voltage applied to the FET. The predetermined input gate-source voltage is, for example, selected for a nominal value of a threshold voltage. A process variation can cause a change in the device threshold voltage such that the FET would tend to draw more, or less, current than desired in a specific design. This would result in a different bias current and device performance than otherwise expected.
In the simplest bias circuits, the bias circuit includes a resistor divider that sets the predetermined input gate-source voltage. The resistor divider provides no compensation for process or power supply variations.
U.S. Pat. No. 5,793,194 to Lewis entitled “Bias Circuit Having Process Variation Compensation and Power Supply Variation Compensation” discloses a current source topology for providing the predetermined input gate-source voltage for the FET that compensates for process and power supply variations. The bias circuit includes a biasing FET operating in saturation mode to produce the bias current, a control circuit including a resistive control path through which a control current is produced to provide the input gate-source voltage for the biasing FET and a compensation circuit in a current source topology. The compensation circuit includes a compensation FET of the same type as the bias FET and formed on the same semiconductor chip, hence subject to the same process variations as the biasing FET. The compensation FET is connected at a node interposed in the resistive control path to bleed current. The compensation FET operating in saturation mode as a current source will draw more or less current at the node, depending upon the same process variations as those that affect the biasing FET. Accordingly, if the process variations would cause the biasing FET to tend to draw more current than design values would indicate, the same process variation will cause the compensation FET to draw more current from the resistive control path. This in turn results in an adjustment of the gate voltage of the biasing FET thus maintaining the bias current of the biasing FET within expected circuit design specifications despite the process variations.
Another example of a bias circuit 10 having process variation compensation in a current source topology is depicted in FIG. 1. The principles of using a compensation FET of the same type as the bias FET and formed on the same semiconductor chip as a current source to alter the current through a resistive control path to provide the gate voltage for the biasing FET are the same as those disclosed by Lewis. In this circuit configuration, the orientations of the drain and source connections of the FETs can be interchanged while still achieving the desired performance. Bias circuit 10 includes a fixed resistor R1 connected between ground potential and the drain of a compensation FET 12. The source of compensation FET 12 is connected through a fixed resistor R2 to a negative voltage supply−Vss. The gate of compensation FET 12 is tied to the negative voltage supply. Compensation FET 12 operates in saturation mode as a current source to produce control current Idscntrl. This current source topology, similar to Lewis, is referred to as “self-biased” because the resistance of R2 is setting/varying the source voltage of compensation FET 12.
The control current Idscntrl drawn through resistor R1 (the resistive control path) sets the gate voltage Vg at the gate of the biasing FET 14. The drain and source of biasing FET 14 are connected to voltage supplies Vd and Vs, respectively. Biasing FET 14 is biased to operate in saturation mode as a current source to produce a predetermined level of bias current Idsbias. The predetermined level of bias current corresponding to a predetermined gate-source voltage Vgs applied to the FET for a given Vth. As the source voltage is fixed, the gate-source voltage Vgs is determined by setting the gate voltage Vg.
The nominal gate voltage Vg is determined for a nominal threshold voltage Vth. If due to process variations the actual threshold voltage Vth>nominal for the n-channel biasing FET. if uncompensated, the level of bias current Idsbias would be less than the designed value. However, because Vth>nominal for the compensation FET, the control current Idscntrl drawn through resistor R1 is less, which makes the gate voltage Vg more positive, which in turn increases the level of bias current Idsbias. Under certain bias conditions and transistor processes, simple current source bias circuits may not be able to maintain an acceptable bias current (i.e., transistor performance) over typical process variations.